This invention relates to the field of portable electronic devices containing microprocessors and more particularly to power saving circuitry therefor.
Along with the increasing use of microprocessors in a wide range of products has come their use in portable products. Many of these are highly sophisticated devices, performing a variety of functions and requiring extensive memory elements; e.g., several random access memories (RAM's) and several programmable memories (PROM's, EROM's or EPROM's). When it is considered that these devices, if operated continually as many must be, consume considerable amounts of power, it becomes apparent that there is a need for power saving methods.
There are, in the prior art, many schemes for powering-down battery supplied devices when full operation is not desired or necessary. One example is shown in U.S. Pat. No. 3,855,576, assigned to the same assignee as is the present invention and which covers a pager receiver wherein a precision oscillator and a counter timer provide a one-fifth duty cycle signal which is utilized when no message is being received and turns off the power for most of the unit during such periods.
In portable units containing microprocessors and their associated memories, it is even more advantageous to be able to reduce power whenever possible since power drain may be unduly high in devices containing EROM's or EPROM's (as in the presently described application) such devices require relatively large amounts of power while being accessed, but can have power removed without any loss of information.